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february 2011 doc id 13169 rev 7 1/35 35 stcf03 high power white led driver with i2c interface features buck-boost dc-dc converter drives one power white led up to 800 ma from 2.7 v to 5.5 v in qfn drives one power white led up to 800 ma from 3.3 v to 5.5 v in bga efficient up to 92% output current control 1.8 mhz typ. fixed frequency pwm synchronous rectification full i2c control operational modes: ? shutdown mode ? shutdown + ntc ? ready mode + auxiliary red led ? flash mode: up to 800 ma ? torch mode: up to 200 ma soft and hard triggering of flash flash and torch dimming with 16 exponential values dimmable red led indica tor auxiliary output internally or externally timed flash operation digitally programmable safety time-out in flash mode led overtemperature detection and protection with external ntc resistor opened and shorted led failure detection and protection chip over temperature detection and protection < 1 a shutdown current packages: ?qfn20 (4 x 4) ? tfbga25 (3 x 3) applications cell phone and smart phone camera flashes/strobe pdas and digital still cameras description the stcf03 is a high efficiency power supply solution to drive a single flash led in camera phone, pdas and other hand-held devices. it is a buck - boost converter to guarantee a proper led current control over all possible conditions of battery voltage and output voltage; the output current control ensure a good current regulation over the forward voltage spread characteristics of the flash led. thanks to the high efficiency of the converter allows having the input current taken from the battery remain under 1.5 a. tfbga25 (3 x 3) qfn20 (4 x 4) table 1. device summary order codes packages packaging STCF03PNR qfn20 (4 x 4 mm) 4500 parts per reel stcf03tbr tfbga25 (3 x 3 mm) 3000 parts per reel www.st.com
contents stcf03 2/35 doc id 13169 rev 7 contents 1 description (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 buck-boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 logic pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2.1 scl, sda pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2.2 trig pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2.3 atn pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2.4 add pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2.5 tmsk pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 i2c bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.6 byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.7 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.8 writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.9 interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.10 writing to multiple registers with incremental addressing . . . . . . . . . . . . 18 7.11 reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.12 reading from multiple registers with incremental addressing . . . . . . . . . 19 8 description of internal registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.1 pwr_on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
stcf03 contents doc id 13169 rev 7 3/35 8.2 trig_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.3 tch_on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.4 ntc_on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.5 ftim_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.6 tdim_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.7 fdim_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.8 auxi_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.9 auxt_0~3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.10 f_run . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.11 led_f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.12 ntc_w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.13 ntc_h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.14 ot_f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.15 voutok_n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.1 poweron reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2 shutdown, shutdown with ntc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.3 ready mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.4 single or multiple flash using exter nal (microprocessor) temporization . 25 9.5 external (microprocessor) temporization using trig_en bit . . . . . . . . . 26 9.6 single flash using internal temporization . . . . . . . . . . . . . . . . . . . . . . . . 26 9.7 multiple flash using internal temporization . . . . . . . . . . . . . . . . . . . . . . . 26 10 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 11 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
list of tables stcf03 4/35 doc id 13169 rev 7 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. list of external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 8. interface protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. i2c register mapping function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. command register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 11. dimming register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 12. auxiliary register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. auxiliary led dimming table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. torch mode and flash mode dimming registers settings . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 15. status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 16. status register details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 17. qfn20 (4 x 4 mm.) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
stcf03 list of figures doc id 13169 rev 7 5/35 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. pin connections (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. procedure for assigning a non-default i2c address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. data validity on the i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. timing diagram on i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 8. acknowledge on i2c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. writing to a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10. writing to multiple register with incremental addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 11. reading from a single register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12. reading from multiple registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13. flash and torch current vs. dimming value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 14. voutok_n behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15. efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 16. i otorch vs. t_dimm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 17. i oflash vs. f_dimm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 18. ioaux vs. auxi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 19. i oflash vs. temp. v i = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 20. vfb2 vs. temp. at i o = 800 ma,v i = 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 21. i q vs. temp. v i = 5.5 v ready-mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 22. start-up in flash mode 800 ma at v i = 3.6 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 23. line transient in flash mode 800 ma, change of v i from 2.7 v to 3.3 v in 10 s . . . . . . . . 28 figure 24. qfn20 (4 x 4 mm.) drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
description (continued) stcf03 6/35 doc id 13169 rev 7 1 description (continued) all the functions of the device are controlled through the i2c which helps bus that allows to reduce logic pins on the package and to save pcb tracks on the board. hard and soft- triggering of flash are both supported. the device includes many functions to protect the chip and the power led such as: a soft start control, chip over temperature detection and protection as well as opened and shorted led detection and protection. besides, a digital programmable time out function protects the led in case of a wrong command from the microprocessor. an optional external ntc resi stor is supported to protect the led against over heating. in mobile phone applications it is possible to reduce immediately the flash led current during the signal transmission using the tmsk pin. this saves battery life and gives more priority to supply rf transmissi on instead of flash function. it is possible by i2c to separately program the current intensity in flash and torch mode using exponential steps. an auxiliary output can cont rol an optional red led to be used as a recording indicator. the device is packaged in qfn (4 x 4 mm) 20l with a height less than 1 mm and in tfbga25 (3 x 3 mm).
stcf03 diagram doc id 13169 rev 7 7/35 2 diagram figure 1. block diagram
pin configuration stcf03 8/35 doc id 13169 rev 7 3 pin configuration figure 2. pin connections (bottom view) tfbga25 (3x3) qfn20 (4x4) table 2. pin description pin n for qfn20 pin n for tfbga25 symbol name and function 1 e1, d2 vlx2 inductor connection 2b3rxr x resistor connection 3 a4 ntc ntc resistor connection 4 d1, c2 vout output voltage 5 b5 fb1 feedback pin [i led *(r fl +r tr )] 6a5fb2r tr bypass 7 b4 fb2s feedback sensing pin [i led *r fl ] 8 e2 gnd signal ground 9 d4 add i2c address selection 10 d5 auxl auxiliary led output 11 c5 tmsk tx mask input. 12 b1, c1 pvbat power supply voltage 13 a3 vbat supply voltage 14 a2 vlx1a inductor connection 15 a1, b2 vlx1b inductor connection 16 e5 scl i2c clock signal 17 e3 sda i2c data 18 c3, d3 pgnd power ground 19 e4 atn attention (open drain output, active low) 20 c4 trig flash trigger input exposed pad pgnd to be connected to the pcb ground plane for optimal electrical and thermal performance
stcf03 maximum ratings doc id 13169 rev 7 9/35 4 maximum ratings table 3. absolute maximum ratings (1) 1. absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these condition is not implied. symbol parameter value unit vbat signal supply voltage -0.3 to 6 v pvbat power supply voltage -0.3 to 6 v vlx1a, vlx1b inductor connection 1 ?0.3 to v i +0.3 v vlx2 inductor connection 2 ?0.3 to v o +0.3 v vout output voltage -0.3 to 6 v auxl auxiliary led ?0.3 to v i +0.3 v fb1, fb2, fb2s feedback and sense voltage -0.3 to 3 v scl, sda, trig, atn, add tmsk logic pin -0.3 to v i +0.3 v r x connection for reference resistor -0.3 to 3 v ntc connection for led temperature sensing -0.3 to 3 v esd human body model 2kv p tot (bga) (2) 2. power dissipation is related parameter to used pcb. the recommended pcb desi gn is included in the application note. continuous power dissipation (at t a =70c) 800 mw t op operating junction temperature range -40 to 85 c t j junction temperature -40 to 150 c t stg storage temperature range -65 to 150 c table 4. thermal data symbol parameter qfn20 tfbga25 unit r thja thermal resistance junction-ambient 59 150 c/w
application stcf03 10/35 doc id 13169 rev 7 5 application **: connect to v i , or gnd or sda or scl to choose one of the 4 different i2c slave addresses. ***: optional components to support auxiliary functions. note: all of the above listed components refer to typical application. operation of the stcf03 is not limited to the choice of these external components. figure 3. application schematic table 5. list of external components component manufacturer part number value size c i tdk x5r0j106m 10 f 0603 c o tdk x5r0j105m 1 f 0603 l (i flash = 0.5a) tdk vlf3012st-4r7mr91 4.7 h 2.6 x 2.8 x 1.2 mm l (i flash = 0.8a) tdk vlf4012at-4r7m1r1 4.7 h 3.7 x 3.5 x 1.2 mm ntc murata ncp21wf104j03ra 100 k 0805 r fl 0.27 0603 r tr 1.8 0402 r x 15 k 0402
stcf03 electrical characteristics doc id 13169 rev 7 11/35 6 electrical characteristics t j = 25 c, v i = 3.6 v, 2 x c i = 10 f, c o = 1 f, l = 4.7 h, r fl = 0.27 , r tr = 1.8 , r x = 15 k , typ. values @ 25 c, unless otherwise specified. table 6. electrical characteristics symbol parameter test cond ition min. typ. max. unit v i input operation supply voltage 2.7 5.5 v v pw_on reset power on reset threshold v i rising 2.3 v i o output current adjustment range i flash flash mode for v i = 2.7 v to 5.5 v (STCF03PNR) 60 800 ma flash mode for v i = 2.7 v to 3.3 v (stcf03tbr) 60 600 flash mode for v i =3.3 v to 5.5 v (stcf03tbr) 60 800 output current adjustment range i torch torch mode v i = 2.7 v to 5.5 v 15 200 auxiliary led output current adjustment range i auxled ready mode, v i = 3.3 v to 5.5 v 0 20 v o regulated voltage range 2.5 5.3 v fb1 feedback voltage torch mode 30 250 mv fb2 feedback voltage flash mode 30 250 mv i o output current tolerance flash mode, i o = 160 mv/r fl -10 10 % r on_ fb1-fb2 on resistance torch mode, i o = 200 ma 90 m i q quiescent current in shutdown mode ntc_on=0 1 a ntc_on=1 1 quiescent current in ready - mode 1.8 ma f s frequency v i = 2.7 v 1.8 mhz efficiency of the chip itself v i = 3.2 to 4.2 v, flash mode, i o = 800 ma 87 % efficiency of the whole application v i = 3.2 to 4.2 v, flash mode, i o = 800 ma, v o =v fled_max + v fb2 = 5.02 v see the typical application schematic it is included losses of inductor and sensing resistor 76 ovp output over voltage protection v i = 5.5 v, no load 5.3 v ov hyst over voltage hysteresis v i = 5.5 v, no load 0.3 v otp over temperature protection v i = 5.5 v 140 c ot hyst over temperature hysteresis v i = 5.5 v 20 c r on t1 rx-ntc switch on resistance ready mode 25
electrical characteristics stcf03 12/35 doc id 13169 rev 7 note: typical value, not production tested. ntc leak rx-ntc switch off leakage shutdown mode, v ntc = 2 v v rx = gnd 1 a v ol output logic signal level low at n i ol = 10 ma 0.2 v i oz output logic leakage current at n v oz = 3.3 v 1 ma v il input logic signal level scl, sda, trig, test, add v i = 2.7 v to 5.5 v 0 0.4 v v ih 1.4 3 t on led current rise time i led = 0 to i led = max 2ms table 6. electrical characteristics (continued) symbol parameter test cond ition min. typ. max. unit
stcf03 introduction doc id 13169 rev 7 13/35 7 introduction the stcf03 is a buck-boost converter, dedicated to power and control the current of a power white led in a camera cell phone. the device operates at a constant switching frequency of 1.8 mhz typ. it provides an output voltage down to 2.5 v and up to 5.3 v, from a 2.7 v to 5.5 v supply voltage. this supply range allows operation from a single cell lithium-ion battery. the i2c bus is used to control the device operation and for diagnostic purposes. the current in torch mode is adjustable from 15 ma to 200 ma. flash mode current is adjustable up to 800 ma, bga version is able to deliver 600 ma at battery range 2.7 v to 3.3 v. the aux led current can be adjusted from 0 to 20 ma. the device uses an external ntc resistor to sense the temperature of the white led. these two last functions may not be needed in all applications, and in these cases the relevant external components can be omitted. 7.1 buck-boost converter the regulation of the pwm controller is done by sensing the current of the led through external sensing resistors (r fl and r tr , see application schematic). depending on the forward voltage of the flash led, the device automatically can change the operation mode between buck (step down) and boost (step up) mode. three cases can occur: boost region (v o > v bat ): this configuration is used in most of the cases, as the output voltage v o = v fled + i led x rfl) is higher than v bat ; buck region (v o < v bat ); buck - boost region (v o ~ v bat ). 7.2 logic pin description 7.2.1 scl, sda pins these are the standard clock and data pins as defined in the i2c bus specification. external pull-up is required according to i2c bus specifications. the recommended maximum voltage of these signals should be 3.0 v. 7.2.2 trig pin this input pin is internally and-ed with the trig_en bit to generate the internal signal that activates the flash operation. this gives to th e user the possibility to accurately control the flash duration using a dedicated pin, avoiding the i2c bus latencies (hard-triggering). no internal pull-up nor pu ll-down is provided. 7.2.3 atn pin this output pin (open-drain, active low) is provided to better manage the information transfer from the stcf03 to the microprocessor. because of the limitations of a single master i2c bus configuration, the microprocessor should regularly poll the stcf03 to verify if certain operations have been completed, or to check diagnostic information. alternatively, the microprocessor can use the atn pin to be advised that new data are available in the stat_reg, thus avoiding continuous polling. then the informatio n can be read in the stat_reg by a read operation via i2c that, besides, automatically resets the atn pin. the stat_reg bits affecting the atn pin status are mapped in ta b l e 1 6 . no internal pull-up is provided.
introduction stcf03 14/35 doc id 13169 rev 7 7.2.4 add pin with this pin it is possible to select one of the 4 possible i2c slave addresses. no internal pull-up nor pull-down is provided. the pin has to be connected either gnd, v i , scl or sda to select the desired i2c slave address (see ta b l e 6 ) when add is connected to gnd the i2c addr ess is assigned automatically while in the other three configurations in which add pin is connected to vbat or sda or scl, the following procedure must be activated in order that the right address is assigned. after applying vbat to the chip, the vbat voltage must be pulled down to gnd for a time longer than 100 ms. after that time the right i2c address is assigned to the chip. this procedure must be repeated every time the vbat voltage is disconnected (see figure 4 below) 7.2.5 tmsk pin this pin can be used to implement the tx masking function. this function has effect only for flash current settings higher than 200 ma (bit fdim_3 = 1). under this condition, when this pin is pulled high by the p, the current flowing in the led is forced at 200 ma typ. no internal pull-up nor pull-down is provided: to be externa lly wired to gnd if tx masking function is not used. table 7. address table add pin a7 a6 a5 a4 a3 a2 a1 a0 gnd0110000r/w vbat0110001r/w sdal0110010r/w scl0110011r/w figure 4. procedure for assigning a non-default i2c address sda line a c k m s b l s b r / w a c k a c k a c k s t o p m s b m s b l s b l s b device address 7 bits w r i t e address of register data ?. scl line s t a r t vbat 100ms address is assigned. the new i2c address can be used for scl and sda sda line a c k m s b l s b r / w a c k a c k a c k s t o p m s b m s b l s b l s b device address 7 bits w r i t e address of register data ?. scl line s t a r t vbat 100ms address is assigned. the new i2c address can be used for scl and sda
stcf03 introduction doc id 13169 rev 7 15/35 7.3 i2c bus interface data transmission from the main microprocessor stcf03 and vice versa takes place through the 2 wires i2c bus interface wires, consisting of the two lines sda and scl (pull-up resistors to a positive supply voltage must be externally connected). the recommended maximum voltage of these signals should be 3.0 v. 7.4 data validity as shown in figure 5 , the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. 7.5 start and stop conditions both data and clock lines remain high when the bus is not busy. as shown in figure 6 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of th e sda line while scl is high. a stop condition must be sent before each start condition. figure 5. data validity on the i2c bus figure 6. timing diagram on i2c bus
introduction stcf03 16/35 doc id 13169 rev 7 7.6 byte format every byte transferred to the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse. any change in the sda line at this time will be interpreted as a control signal. 7.7 acknowledge the master (microprocessor) puts a resistive high level on the sda line during the acknowledge clock pulse (see figure 8 ). the peripheral (stcf03) that acknowledges has to pull-down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. the peripheral which has been addressed has to generate an acknowledge pulse after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse duration. in this case the master transmitter can generate the stop information in order to abort the transfer. the stcf03 won't generate the acknowledge if the v i supply is below the undervoltage lockout threshold. figure 7. bit transfer figure 8. acknowledge on i2c bus
stcf03 introduction doc id 13169 rev 7 17/35 7.8 writing to a single register writing to a single register starts with a start bit followed by the 7 bit device address of stcf03. the 8 th bit is the r/w bit, which is 0 in this case. r/w = 1 means a reading operation. then the master waits for an acknowledge from stcf03. then the 8 bit address of register is sent to stcf03. it is also followed by an acknowledge pulse. the last transmitted byte is the data that is going to be written to the register. it is again followed by an acknowledge pulse from stcf03. then master generates a stop bit and the communication is over. see figure 9 below. 7.9 interface protocol the interface protocol is composed: ? a start condition (start) ? a device address + r/w bit (read =1 / write =0) ? a register address byte ? a sequence of data n* (1 byte + acknowledge) ? a stop condition (stop) table 8. interface protocol device address + r/w bit register address data 76543210 76543210 76543210 s t a r t m s b l s b r w a c k m s b l s b a c k m s b l s b a c k s t o p figure 9. writing to a single register s t a r t device address 7 bits a c k w r i t e m s b l s b r / w a c k address of register data a c k a c k s t o p m s b m s b l s b l s b sda line s t a r t device address 7 bits a c k w r i t e m s b l s b r / w a c k address of register data a c k a c k s t o p m s b m s b l s b l s b s t a r t device address 7 bits a c k w r i t e m s b l s b r / w a c k address of register data a c k a c k s t o p m s b m s b l s b l s b sda line
introduction stcf03 18/35 doc id 13169 rev 7 the register address byte determines the first register in which the read or write operation takes place. when the read or write operation is finished, the register address is automatically increased. 7.10 writing to multiple registers with incremental addressing it would be unpractical to send several times the device address and the address of the register when writing to multip le registers. stcf03 supports wr iting to multiple registers with incremental addressing. when the data is written to a register, the address register is automatically increased, so the next data can be sent without sending the device address and the register address again. see figure 10 below. 7.11 reading from a single register the reading operation starts with a start bit followed by the 7 bit device address of stcf03. the 8 th bit is the r/w bit, which is 0 in this case. stcf03 confirms the receiving of the address + r/w bit by an acknowledge pulse. the address of the register which should be read is sent afterwards and confirmed again by an acknowledge pulse of stcf03 again. then the master generates a start bit again and sends the device address followed by the r/w bit, which is 1 now. stcf03 confirms the receiving of the address + r/w bit by an acknowledge pulse and starts to send the data to the master. no acknowledge pulse from the master is required after receiving the data. then the master generates a stop bit to terminate the communication. see figure 11 . figure 10. writing to multiple register with incremental addressing s t a r t device address 7 bits a c k w r i t e m s b l s b r / w a c k address of register i data i a c k a c k s t o p m s b m s b l s b l s b data i+1 a c k l s b data i+2 a c k l s b data i+2 l s b data i+n a c k m s b m s b m s b m s b m s b a c k l s b sda line s t a r t device address 7 bits a c k w r i t e m s b l s b r / w a c k address of register i data i a c k a c k s t o p m s b m s b l s b l s b data i+1 a c k l s b data i+2 a c k l s b data i+2 l s b data i+n a c k m s b m s b m s b m s b m s b a c k l s b s t a r t device address 7 bits a c k w r i t e m s b l s b r / w a c k address of register i data i a c k a c k s t o p m s b m s b l s b l s b data i+1 a c k l s b data i+2 a c k l s b data i+2 l s b data i+n a c k m s b m s b m s b m s b m s b a c k l s b sda line
stcf03 introduction doc id 13169 rev 7 19/35 7.12 reading from multiple registers with incremental addressing reading from multiple registers starts in the sa me way like reading from a single register. as soon as the first register is read, the regist er address is automatically increased. if the master generates an acknowledge pulse after receiving the data from the first register, then reading of the next register can start immediately without sending the device address and the register address again. the last acknowledge pulse before the stop bit is not required. see the figure 12 . figure 11. reading from a single register s t a r t device address 7 bits a c k w r i t e m s b l s b r / w address of register a c k m s b l s b s t a r t a c k r / w r e a d device address 7 bits data l s b s t o p n o a c k sda line s t a r t device address 7 bits a c k w r i t e m s b l s b r / w address of register a c k m s b l s b s t a r t a c k r / w r e a d device address 7 bits data l s b s t o p n o a c k sda line figure 12. reading from multiple registers s t a r t device address 7 bits a c k w r i t e m s b l s b r / w address of register i a c k m s b l s b s t a r t a c k r / w r e a d device address 7 bits data i a c k s t o p l s b data i+1 a c k l s b data i+2 a c k l s b data i+2 l s b data i+n m s b m s b m s b m s b a c k l s b n o a c k sda line s t a r t device address 7 bits a c k w r i t e m s b l s b r / w address of register i a c k m s b l s b s t a r t a c k r / w r e a d device address 7 bits data i a c k s t o p l s b data i+1 a c k l s b data i+2 a c k l s b data i+2 l s b data i+n m s b m s b m s b m s b a c k l s b n o a c k sda line
description of internal registers stcf03 20/35 doc id 13169 rev 7 8 description of internal registers 8.1 pwr_on when set, it activates all analog and power internal blocks including the ntc supporting circuit, and the device is ready to operate (ready mode). as long as pwr_on=0, only the i2c interface is active, minimizing stand-by mode power consumption. 8.2 trig_en this bit is and-ed with the trig pin to generate the internal signal fl_on that activates flash mode. by this way, both soft-triggering and hard-triggering of the flash are made possible. if soft-triggering (through i2c) is c hosen, the trig pin is not used and must be kept high (vi). if hard-triggering is chosen, then the trig pin has to be connected to a microprocessor i/o devoted to flash timing control, and the trig_en bit must be set in advance. both triggering modes can benefit of th e internal flash time counter, that uses the trig_en bit and can work either as a safety shut-down timer or as a flash duration timer. flash mode can start only if pwr_on=1. led current is controlled by the value set by the fdim_0~3 of the dim_reg. 8.3 tch_on when set from ready mode, the stcf03 enters the torch mode. the led current is controlled by the value set by the tdim_0~3 of the dim_reg. 8.4 ntc_on in ready mode, the comparators that monitor the led temperature are activated if ntc_on bit is set. ntc-related blocks are always active regardless of this bit in torch mode and flash mode. table 9. i2c register mapping function register name sub address (hex) operation cmd_reg 00 r / w dim_reg 01 r / w aux_reg 02 r / w stat_reg 03 r only table 10. command register cmd_reg (write mode) msb lsb sub add=00 pwr_on trig_en tch_on nt c_on ftim_3 ftim_2 ftim_1 ftim_0 power on reset value 0 0 000000
stcf03 description of internal registers doc id 13169 rev 7 21/35 8.5 ftim_0~3 this 4bit register defines the maximum flash duration. it is intended to limit the energy dissipated by the led to a maximum safe value or to leave to the stcf03 the control of the flash duration during normal operation. values from 0~15 correspond to 0~1.5 s (100 ms steps). the timing accuracy is related to the internal oscilla tor frequency that clocks the flash time counter (+/- 20 %). entering flash mode (either by soft or hard triggering) activates the flash time counter, which begins counting down from the value loaded in the f_tim register. when the counter reaches zero, flash mode is stopped by resetting trig_en bit, and simultaneously the atn pin is set to true (low) to alert the microprocessor that the maximum time has been reached. ftim value remains unaltered at the end of the count. 8.6 tdim_0~3 these 4 bits define the led current in torch mode with 16 values fitting an exponential law. max torch current value is 25% of max flash current. ( figure 13 ) 8.7 fdim_0~3 these 4 bits define the led current in flash mode with 16 values fitting an exponential law. the max value of the current is set by the external resistors r fl and r tr . ( figure 13 ) note: led current values refer to r fl =0.27 , r tr =1.8 table 11. dimming register dim_reg (write mode) msb lsb sub add=01 tdim_3 tdim_2 tdim_1 tdim_0 fdim_3 fdim_2 fdim_1 fdim_0 power on, shutdown mode reset value 00000000 figure 13. flash and torch current vs. dimming value current step co efficient - 1.19
description of internal registers stcf03 22/35 doc id 13169 rev 7 8.8 auxi_0~3 this 4 bits register defines the aux led current from 0 to 20 ma. see aux led dimming table for reference. loading any value between 1 and 15 also starts the aux led current source timer, if enabled. the aux led current source is active only in ready mode, and is deactivated in any other mode. 8.9 auxt_0~3 this 4 bit register controls the timer that defines the on-time of the aux led current source. on-time starts when the auxi register is loaded with any value other than zero, and stops after the time defined in the auxt register. values from 1 to 14 of the auxt register correspond to an on-time of the aux led ranging from 100 to 1400 ms in 100 ms steps. the value 15 puts the aux led to the continuous light mode. the activation/deactivation of the aux led current source is controlled using only the auxi register. note: led current values refer to r fl = 0.27 , r tr = 1.8 . table 12. auxiliary register aux_reg (write mode) msb lsb sub add=02 auxi_3 auxi_2 auxi_1 auxi_0 auxt_3 auxt_2 auxt_1 auxt_0 power on, shutdown mode reset value 00 000 000 table 13. auxiliary led dimming table (1) auxi (hex) 0123456789abcdef aux led current [ma] 0.0 1.3 2.6 4.0 5.3 6.6 8.0 9.3 10.6 12.0 13.3 14.6 16.0 17.3 18.6 20.0 1. 20 ma output current is ac hievable only if the supply voltage is higher than 3.3 v. table 14. torch mode and flash mode dimming registers settings t_dim (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f f_dim (hex) 0 1 2 3 4 5 6 7 8 9 a b c d e f led current [ma] 16 19 23 27 32 39 46 55 65 77 92 109 124 147 175 209 248 296 352 418 498 592 705 840 internal step 123456789101112131415161718192021222324 v ref1 [mv] 33 40 47 56 67 80 95 113 134 160 190 227 33 40 47 56 67 79 95 113 134 160 190 227 sense resist. r fl + r tr r fl + r tr r fl + r tr r fl + r tr r fl + r tr r fl + r tr r fl + r tr r fl + r tr r fl + r tr r fl + r tr r fl + r tr r fl + r tr r fl r fl r fl r fl r fl r fl r fl r fl r fl r fl r fl r fl
stcf03 description of internal registers doc id 13169 rev 7 23/35 8.10 f_run this bit is kept high by the stcf03 dur ing flash mode. by checking this bit, the microprocessor can verify if the flash mode is running or has been terminated by the time counter. 8.11 led_f this bit is set by the stcf03 when the voltage seen on the led pin is v ref2 > 5.3 v during a torch or flash operation. this condition can be caused by an open led, indicating a led failure. the device automatically goes into ready mode to avoid damage. internal high frequency filtering avoids false detections. this bit is reset by the stcf03 following a read operation of the stat_reg. 8.12 ntc_w this bit is set high by the stcf03 and the atn pin is pulled down, when the voltage seen on the pin r x exceeds v ref4 = 0.56 v. this threshold corresponds to a warning temperature value at the led measured by the ntc. the device is still o perating, but a warning is sent to the microprocessor. this bit is reset by the stcf03 following a read operation of the stat_reg. 8.13 ntc_h this bit is set high by the stcf03 and the atn pin is pulled down, when the voltage seen on the pin r x exceeds v ref5 . this threshold (1.2v) corresponds to an excess temperature value at the led measured by the ntc. the device is put in ready mode to avoid damaging the led. this bit is reset by the stcf03 following a read operation of the stat_reg. 8.14 ot_f this bit is set high by the stcf03 and the atn pin is pulled down, when the chip over- temperature protection (~140 c) has put the devi ce in ready mode. this bit is reset by the stcf03 following a read operation of the stat_reg. table 15. status register stat_reg (read mode) msb lsb sub add=03 n/a f_run led_f ntc_w ntc_h ot_f n/a voutok_n power on, shutdown mode reset value 0000000 0
description of internal registers stcf03 24/35 doc id 13169 rev 7 8.15 voutok_n this bit is set by the stcf03. it is used to protect the device, if the output is shorted. the voutok_n bit is set to high at the start-up. then a current generator of 20 ma charges the output capacitor for 360 s typ. and it detects when the output capacitor reaches 100 mv. if this threshold is reached the bit is set to low. if the output is shorted to ground or the led is shorted this threshold is never reached: the bit stays high, atn pin is pulled down and the device will not start. this bit is rese t following a read operat ion of the stat_reg. figure 14. voutok_n behavior table 16. status register details bit name f_run (stat_reg) led_f (stat_reg) ntc_w (stat_reg) ntc_h (stat_reg) ot_f (stat_reg) voutok_n (stat_reg) default value 00 0 0 0 0 latched (1) no yes yes yes yes yes forces ready mode when set no yes no yes yes yes sets atn low when set no yes yes yes yes yes 1. yes means that the bit is set by internal signals and is re set to default by an i2c read oper ation of stat_reg no means that the bit is set and reset by internal signals in real-time.
stcf03 detailed description doc id 13169 rev 7 25/35 9 detailed description 9.1 poweron reset this mode is initiated by applying a supply voltage above the v pw_on reset threshold value. an internal timing (~1 s) defines the duration of this status. the logic blocks are powered, but the device doesn't respond to any input. the registers are reset to their default values, the atn and sda pins are in high-z, and the i2c slave address is internally set by reading the add pin configuration. after the internally defined time has elapsed, the stcf03 automatically enters the stand-by mode. 9.2 shutdown, shutdown with ntc in this mode only the i2c interface is alive, accepting i2c commands and register settings. the device enters this mode: automatically from power on reset status; by resetting the pwr_on bit from other operation modes. power consumption is at the minimum (1 a max) if ntc is not activated (ntc_on=0). if pwr_on and ntc_on is set, the t1 is switched on (see the block diagram), allowing the microprocessor to measure the led temperature through its a/d converter. when ntc circuits are active and the v ref-ext is present, the typ. current consumption is increased to 1 a, then it is recommended not to leave the stcf03 in this status if battery drain has to be minimized. 9.3 ready mode in this mode all internal blocks are turned on, but the dc-dc converter is disabled and the white led is disconnected. the ntc circuit can be activated to monitor the temperature of the led and i2c commands and register settings are allowed to be executed immediately. only in this mode the auxiliary led is oper ational and can be turned on and set at the desired brightness using the aux register. the device enters this mode: from stand-by by setting the pwr_on bit; from flash operation by resetting the trig pin or the trig_en bit or automatically from flash operation when the time counter reaches zero; from torch operation by resetting the tch_on bit. the device automatically enters this mode also when an overload or an abnormal condition has been detected during flash or torch operation ( table 16: status register details :). 9.4 single or multiple flash us ing external (microprocessor) temporization to avoid the i2c bus time latency, it is recommended to use the dedicated trig pin to define the flash duration (hard-triggering). the trig_en bit of cmd_reg should be set before starting each flash operation, because it could have been reset automatically in the previous flash operation. flash duration is determined by the pulse length that drives the trig pin. as soon as the flash is activated, the system needs typically 1.2 ms to ramp up the output current on the power led. the internal time co unter will time-out flash operation and keep the led dissipated energy within safe limits in case of software deadlock; ftim register has to be set first, either in stand-by or in ready mode. multiple flashes are possible by strobing the trig pin. time out counter will cumulate ever y flash on-time until the defined time out is reached unless it is reloaded by updating the cmd_reg. if single or multiple flash operation is timed-out, the device automatically goes in ready mode by resetting the
detailed description stcf03 26/35 doc id 13169 rev 7 trig_en bit, and also resets the f_run bit. the atn pin is pulled down to inform the microprocessor that the stat_reg has been updated. 9.5 external (microprocessor) temporization using trig_en bit even if it is possible, it is not recommended to use the trig_en bit to start and stop the flash operation, because of i2c bus latencies: this would result in inaccurate flash timing. nevertheless, if this operation mode is chosen, the trig pin has to be kept high (logic level or wired to v bat ), leaving the whole flash control to the i2c bus. also in this operation mode the time counter will time-out flash operation and keep the led dissip ated energy dissipated by the led within safe limits in case of sw deadlock. 9.6 single flash using internal temporization flash triggering can be obtained either by trig pin (hard-triggering) or by i2c commands (soft-triggering). the first solution is recommended for an accurate start time, while the second is less accurate because of the i2c bus time latency. stop time is defined by the stcf03 internal temporization and its accuracy is determined by the internal oscillator. for hard-triggering it is necessary to set the trig_en bit in advance. for soft-triggering the trig pin has to be kept high (logic level or wired to v bat ) and the flash can be started by setting the ftim and the trig_en through i2c (both are located in the cmd reg). there is a delay time between the moment the flash is triggered and when it appears. this delay is caused by the time necessary to charge up the output capacitor, which is around 1.2 ms depending on battery voltage and output current value. once triggered, the flash operation will be stopped when the time coun ter reaches zero. as soon as the flash is finished, the f_run bit is reset, the atn pin is pulled down for 11 s to inform the microprocessor that the stat_reg has been updated and the device goes back to ready mode. if it is necessary to make a flash longer than the internal timer allows or a continuous flash, then the ftim must be reloaded through i2c bus every time, before the internal timer reaches zero. for example: to get a continuous flash, set ftim to 1.5 s and every 1 s reload the cmd_reg. 9.7 multiple flash using internal temporization this operation has to be processed as a sequence of single flashes using internal temporization starting from hard or soft triggering. since the trig_en bit is reset at the end of each flash, it is necessary to reload the cmd_reg to start the next one.
stcf03 typical performance characteristics doc id 13169 rev 7 27/35 10 typical performance characteristics figure 15. efficiency figure 16. i otorch vs. t_dimm figure 17. i oflash vs. f_dimm figure 18. i oaux vs. auxi figure 19. i oflash vs. temp. v i = 3.3v figure 20. vfb2 vs. temp. at i o = 800ma, v i = 3.3v 0 10 20 30 40 50 60 70 80 90 100 2 2.5 3 3.5 4 4.5 5 5.5 6 v i [v] eff [%] efficiency of the application at io=800ma efficiency of the application at io=55ma 0 10 20 30 40 50 60 70 80 90 100 2 2.5 3 3.5 4 4.5 5 5.5 6 v i [v] eff [%] efficiency of the application at io=800ma efficiency of the application at io=55ma 0 50 100 150 200 250 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 step ma v i = 2.7v v i = 3.6v v i =5.5v 0 50 100 150 200 250 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 step ma v i = 2.7v v i = 3.6v v i =5.5v 0 100 200 300 400 500 600 700 800 900 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 step ma v i 3.3v v i 5.5v 0 100 200 300 400 500 600 700 800 900 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 step ma v i 3.3v v i 5.5v 0 5 10 15 20 25 12345678910111213141516 step ma 0 5 10 15 20 25 12345678910111213141516 step ma 0 100 200 300 400 500 600 700 800 900 -40c 25c 80c temp. ma 0 100 200 300 400 500 600 700 800 900 -40c 25c 80c temp. ma 100 120 140 160 180 200 220 240 260 -40c 25c 80c temp. mv 100 120 140 160 180 200 220 240 260 -40c 25c 80c temp. mv
typical performance characteristics stcf03 28/35 doc id 13169 rev 7 figure 21. i q vs. temp. v i = 5.5 v ready-mode figure 22. start-up in flash mode 800 ma at v i = 3.6 v figure 23. line transient in flash mode 800 ma, change of v i from 2.7 v to 3.3 v in 10 s 0 0.5 1 1.5 2 2.5 3 -40c 25c 85c temp. ma 0 0.5 1 1.5 2 2.5 3 -40c 25c 85c temp. ma trig io i_in io i_in vi
stcf03 package mechanical data doc id 13169 rev 7 29/35 11 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 17. qfn20 (4 x 4 mm.) mechanical data dim. mm. min. typ. max. a 0.80 0.90 1.00 a1 0.02 0.05 b 0.18 0.25 0.30 d 3.85 4.00 4.15 d2 2.55 2.70 2.80 e 3.85 4.00 4.15 e2 2.55 2.70 2.80 e 0.45 0.50 0.55 l 0.30 0.40 0.50 ddd 0.08
package mechanical data stcf03 30/35 doc id 13169 rev 7 figure 24. qfn20 (4 x 4 mm.) drawing 7169619_f
stcf03 package mechanical data doc id 13169 rev 7 31/35 dim. mm. mil s . min. typ. max. min. typ. max. a 1.0 1.1 1.16 39 .4 4 3 . 3 45.7 a1 0.25 9 . 8 a2 0.7 8 0. 8 6 3 0.7 33 . 9 b 0.25 0. 3 00. 3 5 9 . 8 11. 8 1 3 . 8 d2. 93 .0 3 .1 114.2 11 8 .1 122.0 d1 2 7 8 . 8 e2. 93 .0 3 .1 114.2 11 8 .1 122.0 e1 2 7 8 . 8 e0.5 1 9 .7 s e 0.25 9 . 8 tfbga25 mechanical data 75 399 7 9 /a
package mechanical data stcf03 32/35 doc id 13169 rev 7 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n 99 101 3 . 898 3 . 9 76 t 14.4 0.567 ao 4. 3 5 0.171 bo 4. 3 5 0.171 ko 1.1 0.04 3 po 4 0.157 p 8 0. 3 15 tape & reel qfnxx/dfnxx (4x4) mechanical data
stcf03 package mechanical data doc id 13169 rev 7 33/35 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n60 2. 3 62 t 14.4 0.567 ao 3 . 3 0.1 3 0 bo 3 . 3 0.1 3 0 ko 1.60 0.06 3 po 3 . 9 4.1 0.15 3 0.161 p7. 98 .1 0. 3 11 0. 3 1 9 tape & reel tfbga25 mechanical data
revision history stcf03 34/35 doc id 13169 rev 7 12 revision history table 18. document revision history date revision changes 30-jan-2007 1 first release. 27-mar-2007 2 the ovp min. value on table 5 is changed: 5.5 v ==> 5.3 v. 28-aug-2007 3 modified ta b l e 5 . 12-sep-2007 4 modified figure 2 . 10-sep-2008 5 added figure 4 on page 14 . 24-aug-2010 6 updated mechanical data. 23-feb-2011 7 updated mechanical data table 17 on page 29 and figure 24 on page 30 .
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